module SM4_Top (
    input  wire clk_i,
    input  wire rst_n_i,
    
    input  wire key_valid,
    input  wire [127 : 0] key_i,
    input  wire data_valid,
    input  wire [127 : 0] data_i,
    input  wire [1 : 0] mode_i,      //00:密钥拓展 11：加密 01：解密
    output reg key_extend_finished_o,
    output wire data_ready_o,
    output wire [127 : 0] data_o 
);

wire RK_Ready;
wire [1023:0] RK;
wire MK_Valid;
wire Data_Valid;
wire [127:0] Data_o;
wire Enc_en;

assign MK_Valid = (mode_i == 00) & key_valid;
assign Data_Valid = (mode_i[0] == 1'b1) & data_valid;
assign Enc_en = (mode_i[1] == 1'b1);


KeyExp KeyExp0 (
    .clk_i(clk_i),
    .rst_n_i(rst_n_i),

    .MK_Valid_i(MK_Valid),
    .Key_i(key_i),


    .RK_Ready_o(RK_Ready),
    .RoundKey_o(RK)
);

EncDec EncDec0 (
    .clk_i(clk_i),
    .rst_n_i(rst_n_i),
    
    .Mode_i(Enc_en),               //1: enc 0:dec
    .Data_Valid_i(Data_Valid),
    .RoundKey_i(RK),
    .Data_i(data_i),

    .Data_Ready(Data_Ready),
    .Data_o(Data_o) 
);

//output----
always @(posedge clk_i ) begin
    if(!rst_n_i)
        key_extend_finished_o <= 0;
    else if(mode_i == 00) begin
        key_extend_finished_o <= RK_Ready;
    end
end
assign data_ready_o = Data_Ready;
assign data_o = Data_o;


endmodule //SM4_Top
